A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may uses a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
The process of physical design for an IC product is intended to transform logical or circuit descriptions of the product into geometric descriptions, which are referred to as layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins, and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. A list of all or some of the nets in a layout is referred to as a net list.
Routers are a class of EDA tools that defines routes for interconnect lines that connect the pins of nets. To perform routing functions, the routing tool normally receives a previously configured layout of the IC product, e.g., a layout that was created with a “placement” tool. The layout includes numerous geometric objects for the circuit components on the IC. The routing tool will analyze the circuit components on the layout to identify and insert wiring objects to interconnect the circuit components.
To perform routing functions, a router must often work with an “abstracted” version of the layout. Abstracting a layout is the process of converting a potentially complex piece of layout design into an abstracted design, where at least some of the geometries are turned into simplified obstructions. Abstracting layout is a process which is often necessary to ease the task of some EDA engines such as the layout routers.
Working with parameterized cell (pcells) can complicate the process of implementing and using abstracted layouts. With pcells, the designer selects parameters to describe features of electronic components for a design of an integrated circuit. The pcell tool can then automatically generate multiple representations of the electronic components of the pcell based on the parameters. The parameterized data specified by the user is advantageous in that it minimizes the effort of data entry and editing in the design tool.
Any kind of layout data can be parameterized. For example, with a transistor pcell, the length, width, number of gate segments, and other design elements of the transistor, can be realized by simply inserting or changing one or more parameter values. For bipolar designs, parameterized data can include shapes such as arcs and circles. Design data can include text, and the location of the text may be relative to a virtual shape. Also, pieces of parameterized data can automatically appear, disappear, or replicate as a condition of another parameter. To generate a pcell instance, a library name, cell name, instance name, orientation, and the type and values of parameters are specified. The parameters may also be used to set a size of each parameterized cell shape.
However, conventional approaches and systems that implement pcells do not have the capability to adequately or efficiently utilize and maintain abstract pcell variants. To address this problem, embodiments of the present invention provide an improved method, system, and computer program product for utilizing abstracted versions of layout portions in conjunction with parameterized cells (pcells). Other and additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.